The present invention relates generally to non-volatile memory devices and, more particularly, to a method and system of varying the regulated voltage supplied during erase in flash electrically erasable programmable read-only memory (EEPROM) devices.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating-gate transistors in a silicon substrate. A floating-gate transistor is capable of storing electrical charge on a separate gate electrode, known as a floating gate that is separated by a thin dielectric layer from a control-gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
Flash memory is formed by rows and columns of flash transistors, with each transistor being referred to as a cell that includes a control gate, a drain and a source. A cell is typically programmed by applying a predetermined voltage to the control gate, a second predetermined voltage to the drain, and grounding the source. This causes channel hot electrons to be injected from the drain depletion region into the floating gate. A cell can be erased several ways in a flash memory device. In one arrangement, a cell is erased by applying a predetermined voltage to the source and he control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source.
The predetermined voltage applied to the control gate of the cells during an erase operation can be a negative voltage that is generated from a supply voltage (Vcc) using a charge pump. The charge pump is well known in the art as a circuit capable of receiving a relatively small magnitude of input voltage and generating a relatively larger magnitude of positive or negative voltage as an output. The negative voltage generated during the erase operation by the charge pump is typically regulated to a predetermined voltage using some type of comparator. Comparators are also well known in the art as a circuit capable of comparing two variables and providing a predetermined control output indicating the difference between the variables.
In the prior art, the regulation of the negative voltage was fixed such that regulation was to a predetermined negative voltage. Known problems occur during the fabrication stages of the flash memory when it is desirable to vary the predetermined negative voltage generated during erase to test and characterize the cells. Testing and characterization includes identifying the characteristics of cell function, determining the unselected cell disturb during erase and determining the erase speed of the cells. The unselected cell disturb during erase is used to determine if the cells that are not selected to be erased are affected by the predetermined voltages applied during erase. Since the predetermined negative voltage cannot be easily varied in the prior art, testing and characterization of the cells is difficult and time-consuming.
To that end, a need exists for methods and systems that can be used to easily vary the regulation of the negative voltage generated during erase of the cells in a memory device.
The present invention discloses a method of generating a predetermined erase voltage in a memory device that overcomes the problems associated with the prior art. In the preferred embodiment, the memory device is a flash memory that includes a reference voltage circuit, a regulator circuit, a low-supply voltage negative charge pump, at least one decoder circuit and at least one wordline. The reference voltage circuit is electrically connected with the regulator circuit. The regulator circuit is electrically connected with a negative potential line (NEGP) that electrically connects the low-supply voltage negative charge pump with the decoder circuits. The decoder circuits are electrically connected with the wordlines.
During operation of the preferred flash memory in a negative gate stress mode, a variable reference voltage is generated with the reference voltage circuit. The variable reference voltage is generated by an external power supply whose output can be manually varied in a first predetermined voltage range. The variable reference voltage is directed to the regulator circuit, which generates a predetermined initializing voltage in response to the variable reference voltage. The initializing voltage is stored in a plurality of capacitors within the regulator circuit.
When an erase is initiated during the negative gate stress mode, the regulator circuit that has been previously initialized by the variable reference voltage is electrically isolated from the reference voltage circuit. The low-supply voltage negative charge pump is activated to generate and direct a relatively high negative voltage to the negative potential line (NEGP). The relatively high negative voltage present on the negative potential line (NEGP) is regulated by the regulator circuit to a predetermined erase voltage based on the variable reference voltage. The predetermined erase voltage is directed to the decoder circuits that are activated to transfer the predetermined erase voltage to a plurality of wordlines.
Regulation of the relatively high negative voltage occurs when the low-supply voltage negative charge pump is pumping the magnitude of voltage on the negative potential line (NEGP) down to the relatively high negative voltage. Since the capacitors within the regulator circuit are electrically connected with the negative potential line (NEGP), as the magnitude of voltage is pumped more negative by the low-supply voltage negative charge pump, the capacitors are correspondingly discharged. When the capacitors are discharged to about zero volts, a supply voltage connection (Vcc) is electrically connected with the negative potential line (NEGP) by the regulator circuit. The regulator circuit acts as a shunt regulator such that the additional current produced by the low-supply voltage negative charge pump after the capacitors are discharged is pulled up to the supply voltage connection (Vcc). The magnitude of the predetermined erase voltage is thereby prevented from being pumped further negative.
Since the variable reference voltage supplied from the reference voltage circuit determines the predetermined erase voltage, variation of the variable reference voltage within the first predetermined voltage range will produce different predetermined erase voltages. When an erase operation begins, the variable reference voltage circuit has previously initialized the regulator circuit with the variable reference voltage and the regulator circuit is electrically isolated from the reference voltage circuit. As such, the only discharge path for the capacitors that are charged to the initializing voltage is through the negative potential line (NEGP).
Another preferred embodiment of the present invention is a voltage regulation system for use during an erase operation in a memory device that, in the preferred embodiment, is a flash memory. During operation in a negative gate stress mode, when an erase operation is initiated, a low-supply voltage negative charge pump generates a relatively high negative voltage. A regulator circuit that is electrically connected with the low-supply voltage negative charge pump regulates the relatively high negative voltage to a predetermined erase voltage. The predetermined erase voltage is then transferred to a plurality of wordlines. The predetermined erase voltage is based on a variable reference voltage generated by a reference voltage circuit electrically connected with the regulator circuit. The variable reference voltage initializes the regulator circuit to control the regulation of the predetermined erase voltage in a similar fashion to the previously set forth preferred embodiment.
The ability to vary the initializing voltage allows a plurality of cells within the wordlines of the flash memory to be characterized by using different predetermined erase voltages to perform the erase operation. In prior art memory devices, the initializing voltage cannot be easily varied and therefore characterization of the erase speed, the unselected cell erase disturb and other operating parameters is difficult. Using the preferred embodiment of the present invention, the previously time-consuming and difficult task of testing or adjusting the cell function is accomplished quickly and easily.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.